To illustrate, we’ll look at unit tests that verify the memory write transactions derived from streaming AXI4 bus input. To get a feel for unit test granularity, I find low level tests easiest to write because the scope of possible input conditions and outcomes is narrow. This is why I say it’s the most important skill I’ve ever learned 🙂. I’ve unit tested UVM test bench components for years and the before/after difference in code quality is truly night and day. (Note that ‘magical’ is not hyperbole here. Verification engineers get RTL that magically works block and chip level verification runs much more smoothly and predictably as a result. The benefit of unit testing is flushing out low-level, hard-to-find bugs in RTL as you write it, way before anyone else sees them.

Unit testing preempts tradition with a 3rd tier unit test each individual module in isolation first, then integrate those modules into sub-systems and corresponding chip.

Traditionally, verification targets chip and sub-system hierarchies the chip level tier for integration testing and sub-system tier for exhaustive functional testing. But which is the better option? A Unit Testing Primer Both are productive first steps for verifying low-level RTL functionality. Then a few weeks ago I saw the power of formal property checking with Questa® PropCheck and suddenly feel conflicted. In fact, I regularly say unit testing is one of the most important engineering skills I’ve ever learned. I’ve been big on unit testing for a little over 10 years.

Formal property verification